1. Technical Field of the Invention
The present invention relates to the field of integrated circuits, and more particularly to low-cost lithography.
2. Related Arts
Lithography is the process of creating patterns in an IC layer. It involves mask fabrication, lithographic and related processes. With the advancement of integrated circuits, masks become more and more expensive. At the 0.13 μm node, a conventional mask costs ˜$30,000, and well over $100,000 for a phase-shift mask (PSM); a typical mask set costs ˜$1 million. For medium-to small-volume production, mask cost becomes a significant portion of the overall IC cost. The present invention particularly addresses the lithographic costs associated with opening-related patterns (e.g. inter-level connection and segmented-line), high-precision mask (e.g. OPC-mask and PSM), SCIC (semi-custom IC) and ASIC (application-specific IC), and others.
Before proceeding further, a clarification needs to be made here: the size, dimension, width, length used throughout this disclosure could be either a size, dimension, width, length on wafer, or a size, dimension, width, length on mask. They are, in general, not specified, but should become apparent from the context. For example, no extra efforts have been made to distinguish the minimum feature size on wafer Fw from the corresponding minimum feature size on mask Fm (Fm=Fw×R, where R is the image-reduction ratio of the reduction stepper). They are both referred to as F throughout this disclosure. In the context of wafer pattern (patterns on wafer), F means Fw; in the context of mask pattern (patterns on mask), F means Fm.
1. Opening-Related Patterns
Opening-related pattern refers to the pattern at which an opening is formed in the photoresist during its manufacturing process. There are many types of opening-related patterns in an integrated circuit. The most common ones are inter-level connections and segmented-lines.
FIGS. 1A–1B illustrate a conventional inter-level connection (i.e. physical connection 50va between upper-and lower-metal lines 162, 174). It is a 1F-via 50va, i.e. its dimension (Dv) is equal to or less than 1F, which is the minimum width (Dm, D1) of metal lines 162, 174. The 1F-via requires precise control over the shape of the opening on the mask (mask opening). Accordingly, the mask fabrication needs expensive equipment (e.g. e-beam writing). In addition, this type of bordered via (i.e. via 50va is completely encompassed by the overlapping area of metal lines 162, 174) has small overlay tolerance. It incurs a high processing cost.
FIG. 1BB illustrates a segmented-line 161S. As a comparison, a continuous line 161C is illustrated in FIG. 1BA. This segmented-line 161S comprises two segments 161′, 161″ separated by a segment-gap 161g. This segment-gap 161g is, in fact, a form of opening (referring to FIG. 26). Note that the segments 161′, 161″ have the same width and if the segment 161′ is extended to the right, it preferably coincides with the segment 161″.
2. High-Precision Mask
High-precision masks such as OPC-mask (optical proximity correction) and PSM (phase-shift mask) are developed to extend optical lithography beyond the range of conventional imaging. Both provide the first-order correctional structures to mask patterns. The OPC adds serifs to mask features to recover the loss of shape fidelity due to diffraction and the PSM adds phase-shifter to mask features in such a way that pattern diffraction is partly cancelled. As a result, the imaged wafer patterns have more desired shapes. The correctional structures used by the OPC and the PSM are in direct contact with the zero-order pattern (the mask pattern that forms the majority portion the wafer pattern). Details on OPC and PSM can be found on “Silicon Processing for the VLSI Era”, Vol. 1, 2nd Ed., by Wolf and Tauber, pp. 628–37. Both techniques add significant cost to lithography.
3. Semi-Custom Integrated Circuit (SCIC)
In an SCIC, customers are only involved in the design of a limited number of layers. SCIC manufacturers stock a large number of base wafers. On base wafers, only transistor patterns are finished. Interconnects between transistors are not processed until customer inputs are received. There are two key concepts in SCIC: one is SCIC family; the other is SCIC product. A SCIC family comprises a number of SCIC products. In a SCIC product, all chips have the same transistor and interconnect patterns; in a SCIC family, all SCIC products have the same transistor pattern, but chips from different SCIC products may have different interconnect pattern. The patterns used in SCIC include common patterns and custom patterns: the common patterns are shared in a SCIC family and created by common masks; the custom patterns are only used in a single SCIC product and conventionally created by custom masks. In the memory world, one exemplary SCIC is read-only memory (ROM); in the logic world, one exemplary SCIC is programmable gate-array (PGA).
In a ROM, memory cell could be located at the intersection of horizontal and vertical metal lines. The bit stored in a memory cell is represented through the existence or absence of a via. Accordingly, vias are referred to as info-vias. The via configurations of FIGS. 1CA–1CB, if used in ROM, represent two ROM products: in FIG. 1CA, ROM cells 93, 94 represent “0”, “1”, whereas, “1”, “0” in FIG. 1CB. One ROM of particular interest is three-dimensional read-only memory (3D-ROM), which is disclosed in U.S. Pat. No. 5,835,396. In the 3D-ROM, there is a 3D-ROM layer (a.k.a. quasi-conduction layer) between said vertical and horizontal lines (referring to FIG. 4 of U.S. Pat. No. 5,835,396).
In PGA, the connections between metal lines are configured by vias. Accordingly, vias are referred to as config-vias. If used in PGA, the via configuration of FIGS. 1CA–1CB creates two metal connections: in FIG. 1CA, horizontal line 162 is connected with vertical line 174, whereas, in FIG. 1CB, it is connected with vertical line 173.
In PGA, routings can be configured through metal-line segmentation. For example, if the metal mask of FIG. 1BB is used, the gap 161g will segment the metal line 161S into two segments 161′, 161″, each of which can be used for separate routing and has smaller capacitive load; on the other hand, if the metal mask of FIG. 1BA is used, the metal line 161C will be a continuous line. The metal lines of FIGS. 1BA–1BB can be used in different configurations.
4. Application-Specific Integrated Circuit (ASIC)
In general, ASIC is small and fast. In prior arts, all masks used in an ASIC product are custom masks. The large number of custom masks makes medium-to small-volume ASIC expensive. Even in the shuttle programs provided by several foundries, a 5 mm×5 mm chip costs ˜$75,000. This price tag is difficult to accept for most design-houses.
5. Fabrication of Conventional Mask and Master Optical Disc
In the prior art, the fabrication of a conventional mask is similar to lithographic process in IC. First, photoresist is coated on mask blank, and exposed by e-beam. Then the undesired Cr film is etched away. It is time-consuming and expensive. For PGA, ROM and others, the mask-making should take advantage of the fact that typical openings in these devices are regularly sized and spaced. The opening masks for these devices can be made in a shorter time and at a lower cost.
Optical discs, such as CD, VCD, DVD, have a huge consumer market. An optical disc is fabricated by pressing a master optical disc on a disc blank. Currently, the fabrication of master optical disc is similar to the fabrication of mask in IC. It is time-consuming and expensive.